CSE_211_MCQ_UNIT_5_6

Question 1

The number of micro-operations required to fetch an instruction from memory is __________.

Answer: The number of micro-operations required to fetch an instruction from memory is 2.

Question 2

Consider a 5-stage pipeline with IF, ID, EX, MEM, and WB latencies of 8, 6, 4, 6, and 4 respectively (in ns). If the IF stage is made 50% faster, the percentage it will improve the CPU's performance is:

(a) 12.2
(b) 13.2
(c) 14.3
(d) 15.3

Correct Option: (c) 14.3
Explanation: Performance improvement is calculated by reducing the latency of the IF stage by 50% and evaluating the total cycle time.

Question 3

A certain architecture supports indirect, direct, and register addressing modes. Which of the following cannot be achieved with a single instruction?

(a) Specifying a register number as a source operand.
(b) Specifying a register as the destination operand.
(c) Specifying an immediate value as an operand.
(d) Specifying a memory location as a source operand.

Correct Option: (c)
Explanation: Direct specification of immediate values may not always be supported in specific instruction formats.

Question 4

Consider the following statements:

S1: The RISC processor has CPI always 1.
S2: In horizontal instruction control, signals are always encoded.
S3: In vertical instruction control, signals are encoded.
S4: Vertical instruction is slower than horizontal.

Which statements are true?

(a) S1, S2, S3
(b) S1, S3, S4
(c) S2, S3, S4
(d) None

Correct Option: (b)
Explanation: RISC achieves near CPI=1 under ideal conditions, vertical encoding leads to slower decoding than horizontal.

Question 5

Match the following lists:
List-I | List-II
A. Pointer | 1. Indirect addressing
B. Position-independent code | 2. Immediate addressing
C. Constant operand | 3. Relative addressing

Options:

(a) 3, 2, 1
(b) 1, 3, 2
(c) 2, 3, 1

Correct Option: (b)
Explanation: Pointer corresponds to indirect addressing, position-independent code is achieved via relative addressing, and constant operands use immediate addressing.

Question 6

In which addressing mode is the content of the program counter added to the address part of the instruction to get the effective address?

(a) Implied mode
(b) Relative mode
(c) Register mode

Correct Option: (b) Relative mode
Explanation: Relative mode adds the content of the PC to an offset to calculate the effective address.

Question 7

A pipelined CPU has a speedup of 4.5 over a non-pipelined CPU and has an efficiency of 90%. How many stages are there?

(a) 4
(b) 5
(c) 6
(d) 7

Correct Option: (b) 5
Explanation: Speedup $S = \frac{k}{1 + \text{stall cycles}}$ , where $k$ is the number of stages and efficiency helps deduce $k$ .

Question 8

Which of the following keeps track of the instruction execution sequence?

(a) Accumulator
(b) Program Counter
(c) Stack Pointer
(d) All of the mentioned

Correct Option: (b) Program Counter
Explanation: The Program Counter (PC) holds the address of the next instruction to be executed.

Question 9

A 5-stage pipeline has stages IF, ID, EX, MEM, and WB. For the following program, what is/are the possible hazards?

css
MOV R1, A;   R1 ← μ[A]  
MOV R2, B;   R2 ← μ[B]  
ADD R1, R2;  R1 ← R1 + R2  
MOV X, R1;   μ[X] ← R1

(a) Data Hazard
(b) Control Hazard
(c) Structural Hazard

Correct Option: (a) Data Hazard
Explanation: Dependencies between instructions (e.g., reading and writing the same registers) cause data hazards.

Question 10

In absolute addressing mode, which statement is correct?

The operand is inside the instruction.
The address of the operand is inside the instruction.
The register containing the address of the operand is specified inside the instruction.
The location of the operand is implicit.

(a) 1
(b) 2
(c) 3
(d) 4

Correct Option: (b) 2
Explanation: In absolute addressing, the address of the operand is directly specified in the instruction.

Question 11

Which of the following addressing modes permits relocation without any changes in the code?

(a) Indirect addressing
(b) Indexed addressing
(c) Base register addressing
(d) PC relative addressing

Correct Option: (d) PC relative addressing
Explanation: PC relative addressing uses offsets based on the Program Counter, allowing relocation without code modification.

Question 12

Which one is correct?

The aim of pipelined architecture is to execute one complete instruction in one clock cycle.
The aim of pipelining is to maintain CPI ≈ 1.
Practically, it is not possible to achieve CPI ≈ 1 due to delays introduced by registers.

(a) 1, 2
(b) 2, 3
(c) 3, 1

Correct Option: (b) 2, 3
Explanation: While CPI ≈ 1 is the goal, practical limitations, such as register delays, make this difficult to achieve.

Question 13

Which one is correct?

The maximum speedup that can be achieved is equal to the number of stages.
Practically, efficiency is always less than 100%.
Therefore, speedup is always greater than the number of stages in pipelined architecture.

(a) 1, 2
(b) 2, 3
(c) 3, 1

Correct Option: (a) 1, 2
Explanation: The maximum speedup is limited by the number of stages. Efficiency losses ensure practical speedup is less than theoretical.

Question 14

In the case where only one instruction is executed:

Non-pipelined execution gives better performance than pipelined execution.
This is because delays are introduced due to registers in pipelined architecture.

(a) 1 is true, and 2 is the correct explanation.
(b) 1 is false, but 2 is the correct explanation.
(c) 1 is false, and 2 is also false.

Correct Option: (a) 1 is true, and 2 is the correct explanation.
Explanation: For a single instruction, pipeline registers introduce overhead, making non-pipelined execution faster.

Question 15

High efficiency of a pipelined processor is achieved when:

All stages are of different durations.
There are no conditional branch instructions.
There are no interrupts.
There are no register and memory conflicts.

(a) 1, 2, 3
(b) 2, 3, 4
(c) 3, 4, 1

Correct Option: (b) 2, 3, 4
Explanation: Conditional branches, interrupts, and conflicts reduce pipeline efficiency by causing stalls.

Question 16

Consider a 5-stage pipeline {IF, ID, EX, MA, WB} with clock cycles for instruction 1 as {2, 3, 4, 2, 1}. At which clock does the MA stage complete execution?
Answer: 4th clock cycle.

Correct Option: 4th
Explanation: The completion depends on the latency of each stage and its order in the pipeline.

Question 17

A pipelined CPU has a speedup of 4.5 over a non-pipelined CPU and has an efficiency of 90%. How many stages are there?

(a) 5
(b) 4
(c) 6
(d) 3

Correct Option: (a) 5
Explanation: Speedup = Efficiency × Number of stages, solving for the number of stages gives us 5.

Question 18

A 2-way set associative cache is 256 Kbytes in size. What is the number of sets if the block size is 16 bytes?

(a) 4096
(b) 8192
(c) 1024
(d) 16,384

Correct Option: (a) 4096
Explanation: The total cache size is 256 Kbytes, and with a block size of 16 bytes, the number of sets is calculated as $\frac{256 \times 1024}{16 \times 2} = 4096$ .

Question 19

A cache has a 60% hit ratio for read operations. The cache access time is 30 ns, and the main memory access time is 100 ns. 50% of operations are read operations.
What will be the average access time for read operations?

(a) 50 ns
(b) 58 ns
(c) 100 ns
(d) 70 ns

Correct Option: (b) 58 ns
Explanation: Average access time = Hit ratio × Cache time + Miss ratio × (Cache time + Memory time).
$0.6 \times 30 + 0.4 \times (30 + 100) = 58 \, \text{ns}$ .

Question 20

A CPU has a 30-bit memory address and a 512 Kbyte cache organized into an 8-way set associative cache with a block size of 32 bytes.
What is the number of bits required in the TAG for comparator matching?

(a) 16
(b) 11
(c) 17
(d) 14

Correct Option: (c) 17
Explanation: The number of bits for TAG is calculated as the total address bits minus the bits for index and block offset.
Address bits = 30, Cache size = 512 Kbytes, Block size = 32 bytes, Set associativity = 8-way.
Thus, 17 bits are needed for the TAG.

Question 21

More than one word is put in one cache block to:

(a) Exploit temporal locality references in a program
(b) Exploit spatial locality references in a program
(c) Reduce miss penalty
(d) All of these

Correct Option: (d) All of these
Explanation: Cache blocks with multiple words exploit spatial locality and reduce the miss penalty by fetching adjacent data that may be accessed soon.

Question 22

An instruction pipeline consists of 4 stages: fetch (F), decode (D), execute (E), and write (W).
At what clock cycle will instruction I3 complete its decoding?

(a) 6th clock cycle
(b) 7th clock cycle
(c) 12th clock cycle
(d) 13th clock cycle

Correct Option: (b) 7th clock cycle
Explanation: The decoding stage is completed at the 7th clock cycle for instruction I3, considering the pipeline schedule.

Question 23

How many cycles are required for a 100 MHz processor to execute a program which requires 5 seconds of CPU time?

(a) 109 cycles
(b) 50 × 10⁷ cycles
(c) 10⁸ cycles
(d) 50 cycles

Correct Option: (b) 50 × 10⁷ cycles
Explanation: The number of cycles = CPU time × Processor frequency.
$5 \, \text{seconds} \times 100 \times 10^6 = 50 \times 10^7 \, \text{cycles}$ .

Question 24

Main difference between CISC and RISC is:

(a) RISC has fewer instructions
(b) RISC has fewer addressing modes
(c) CISC has fewer registers
(d) Both (a) & (b)

Correct Option: (d) Both (a) & (b)
Explanation: CISC has a complex instruction set with many addressing modes, while RISC has a simpler instruction set and fewer addressing modes.

Question 25

Which of the following may not definitely occur in an instruction cycle?
(i) Fetch cycle
(ii) Execution cycle
(iii) Indirect cycle

(a) (i) only
(b) (i) and (ii)
(c) (iii) only
(d) (ii) and (iii)

Correct Option: (c) (iii) only
Explanation: The indirect cycle may not occur if the instruction doesn't involve an indirect addressing mode.

Question 26

Most relevant addressing mode to write position-independent code is:

(a) Direct
(b) Indirect
(c) Relative
(d) Indexed Mode

Correct Option: (c) Relative
Explanation: Position-independent code uses relative addressing to enable the code to run at any address without modification.

Question 27

Which set of instruction transfers the memory word specified by the effective address to AC or Load to AC?

(a) DR←M[AR] AC←AC+DR, E←COUT, SC←O
(b) DR←M[AR] AC←DR, SC←O
(c) M[AR]←AC, SC←O
(d) DR←M[AR] AC←AC∧DR, SC←O

Correct Option: (b) DR←M[AR] AC←DR, SC←O
Explanation: This set of instructions correctly loads the accumulator (AC) with the data from memory, as specified by the effective address.

Question 28

A program consists of four major types of instructions. The instruction mix and the CPI for each instruction type are given.
If the clock frequency of the processor is 400 MHz, what is the average CPI of the processor?

(a) 3.75
(b) 2.87
(c) 1.87
(d) 1.54

Correct Option: (b) 2.87
Explanation: The average CPI is calculated by weighted averaging based on the instruction mix and the CPI for each instruction type.

Question 29

Consider a 16-bit processor in which the following one-address instruction is loaded in main memory.
The effective address using PC-relative addressing mode when the processor is executing an instruction at location 300 is ______.
Answer: The effective address depends on the instruction format, offset, and the current PC value.

Question 30

(a) 14.3
(b) 15.3
(c) 16.3
(d) 17.3

Correct Option: (a) 14.3
Explanation: Reducing the IF stage's latency by 50% improves performance by approximately 14.3%, calculated based on the new cycle time.

Question 31

Consider a 4-stage pipeline (IF, ID, EX, WB) with the following latencies:

IF = 5 ns
ID = 6 ns
EX = 7 ns
WB = 4 ns

What is the effective cycle time of the pipeline?

(a) 5 ns
(b) 6 ns
(c) 7 ns
(d) 8 ns

Correct Option: (c) 7 ns
Explanation: The cycle time is determined by the longest latency in the pipeline, which is 7 ns in this case.

Question 32

Which of the following pipelining issues occurs when different stages of the pipeline are unable to operate simultaneously due to resource conflicts?

(a) Structural hazard
(b) Data hazard
(c) Control hazard
(d) Stalling

Correct Option: (a) Structural hazard
Explanation: Structural hazards occur when there are not enough resources (like functional units) to support concurrent operations in the pipeline stages.

Question 33

In which of the following scenarios does the non-pipelined execution perform better than pipelined execution?

(a) When there is a high instruction dependency
(b) When multiple instructions are independent
(c) When there are no data hazards
(d) When there is no branching in the code

Correct Option: (a) When there is a high instruction dependency
Explanation: When instructions have high dependency, pipelining introduces stalls, which may lead to worse performance compared to non-pipelined execution.

Question 34

Which of the following is true about vector processors?

(a) They are designed to handle scalar instructions.
(b) They process multiple data elements in a single instruction cycle.
(c) They require fewer registers compared to scalar processors.
(d) They are less efficient for data parallelism.

Correct Option: (b) They process multiple data elements in a single instruction cycle.
Explanation: Vector processors are optimized to handle vector (multiple data elements) in parallel, making them highly efficient for vector-based operations.

Question 35

Which of the following addressing modes involves adding an offset to the content of the Program Counter (PC)?

(a) Direct addressing
(b) Indexed addressing
(c) PC-relative addressing
(d) Base register addressing

Correct Option: (c) PC-relative addressing
Explanation: In PC-relative addressing, the address of the operand is calculated by adding an offset to the current value of the Program Counter (PC).

Question 36

What is the maximum speedup achievable by pipelining with a 5-stage pipeline?

(a) 5
(b) 4
(c) 1
(d) 10

Correct Option: (a) 5
Explanation: The maximum speedup achievable is equal to the number of stages in the pipeline under ideal conditions (without hazards and stalls).

Question 37

Which of the following is a characteristic of Reduced Instruction Set Computers (RISC)?

(a) Complex instructions with multiple addressing modes
(b) A small set of simple instructions executed in a single cycle
(c) Higher number of cycles per instruction (CPI)
(d) Large instruction set with variable lengths

Correct Option: (b) A small set of simple instructions executed in a single cycle
Explanation: RISC processors are designed for simplicity, with a small instruction set where most instructions execute in one cycle.

Question 38

Consider the following pipeline stages:

IF: Instruction Fetch
ID: Instruction Decode
EX: Execution
MEM: Memory Access
WB: Write Back

What type of hazard is created when one instruction tries to write a register while another instruction needs that register as a source?

(a) Data hazard
(b) Control hazard
(c) Structural hazard
(d) Stale hazard

Correct Option: (a) Data hazard
Explanation: Data hazards occur when there is a dependency on the data that has not yet been written back to the register file.

Question 39

Which of the following techniques is used to resolve data hazards in a pipelined processor?

(a) Branch prediction
(b) Data forwarding
(c) Pipelining
(d) Virtual memory

Correct Option: (b) Data forwarding
Explanation: Data forwarding (or bypassing) is a technique used to resolve data hazards by passing the result of an operation directly to the next stage without waiting for it to be written back.

Question 40

Which of the following is a limitation of pipelined architecture?

(a) It increases the cycle time for instructions.
(b) It reduces the hardware complexity.
(c) It increases the clock frequency.
(d) It may introduce pipeline hazards that affect performance.

Correct Option: (d) It may introduce pipeline hazards that affect performance.
Explanation: Pipeline hazards (data, control, and structural) can introduce delays and reduce the overall performance of pipelined processors.

Question 41

Which of the following terms refers to the situation where multiple instructions are being executed simultaneously, but not necessarily in parallel, in a superscalar processor?

(a) Instruction parallelism
(b) Instruction-level parallelism
(c) Thread-level parallelism
(d) Task-level parallelism

Correct Option: (b) Instruction-level parallelism
Explanation: Instruction-level parallelism (ILP) refers to the parallel execution of multiple instructions in a superscalar processor.

Question 42

Which of the following is NOT an advantage of using cache memory?

(a) Faster data access
(b) Reduces memory access time
(c) Provides higher capacity than main memory
(d) Reduces the bottleneck between CPU and main memory

Correct Option: (c) Provides higher capacity than main memory
Explanation: Cache memory has a small size compared to main memory, and its purpose is to store frequently used data to improve access speed.

Question 43

Which of the following cache replacement policies replaces the cache block that has not been used for the longest time?

(a) FIFO (First-In, First-Out)
(b) LRU (Least Recently Used)
(c) LFU (Least Frequently Used)
(d) Random replacement

Correct Option: (b) LRU (Least Recently Used)
Explanation: LRU replaces the cache block that has been unused for the longest period, assuming that data used recently will be used again soon.

Question 44

What is the purpose of a branch predictor in a pipelined processor?

(a) To reduce the number of cycles per instruction (CPI)
(b) To predict the outcome of conditional branches to avoid pipeline stalls
(c) To optimize cache performance
(d) To predict memory access time

Correct Option: (b) To predict the outcome of conditional branches to avoid pipeline stalls
Explanation: A branch predictor helps minimize the penalty of branch instructions by predicting the likely path and keeping the pipeline filled.

Question 45

Which of the following instructions is NOT typically supported by RISC architectures?

(a) Load
(b) Store
(c) Multiply
(d) Compare

Correct Option: (d) Compare
Explanation: RISC architectures typically avoid complex instructions like compare, focusing on simpler load/store operations and arithmetic.

Question 46

In a pipelined processor, which of the following methods is used to handle control hazards?

(a) Data forwarding
(b) Branch prediction
(c) Cache memory
(d) Instruction reordering

Correct Option: (b) Branch prediction
Explanation: Branch prediction is used to predict the direction of branches to avoid control hazards and keep the pipeline full.

Question 47

Which of the following methods helps to improve memory performance in pipelined architectures?

(a) Pipelining memory accesses
(b) Data forwarding
(c) Increasing the memory size
(d) Reducing the number of pipeline stages

Correct Option: (a) Pipelining memory accesses
Explanation: Memory pipelining helps reduce memory access time by allowing multiple memory operations to occur in parallel, improving overall performance.

Question 48

Which of the following is true for a vector processor?

(a) It processes data in parallel across multiple functional units.
(b) It can only handle scalar data.
(c) It performs only integer arithmetic.
(d) It executes one instruction per clock cycle.

Correct Option: (a) It processes data in parallel across multiple functional units.
Explanation: Vector processors are optimized for parallel processing of vector data, allowing them to process multiple data elements in a single instruction.

Question 49

Which of the following types of hazards are resolved by instruction reordering in a compiler?

(a) Control hazards
(b) Data hazards
(c) Structural hazards
(d) All of the above

Correct Option: (b) Data hazards
Explanation: Instruction reordering can help resolve data hazards by rearranging instructions to avoid dependencies.

Question 50

Which of the following is an example of a non-volatile memory type used to store data permanently?

(a) RAM
(b) Flash memory
(c) Cache memory
(d) Register

Correct Option: (b) Flash memory
Explanation: Flash memory is non-volatile, meaning it retains data even when power is turned off, making it ideal for permanent data storage.

Question 51

Which of the following instructions is typically used in RISC processors to perform operations directly on memory?

(a) Load
(b) Store
(c) Multiply
(d) Compare

Correct Option: (a) Load
Explanation: RISC processors typically use load and store instructions to access memory, while other operations are performed directly on registers.

Question 52

In a 3-way set associative cache with a block size of 32 bytes, how many sets are there in a cache of 256 Kbytes?

(a) 8192
(b) 4096
(c) 1024
(d) 512

Correct Option: (a) 8192
Explanation: Number of sets = Total cache size / (Block size × Associativity) = $\frac{256 \times 1024}{32 \times 3} = 8192$ .

Question 53

In a superscalar processor, multiple instructions are executed simultaneously, but if two instructions have a dependency on the same resource, it can lead to:

(a) Structural hazard
(b) Data hazard
(c) Control hazard
(d) Resource hazard

Correct Option: (a) Structural hazard
Explanation: Structural hazards occur when there are not enough resources (like execution units) to execute multiple instructions simultaneously.

Question 54

Which of the following optimizations is used to minimize pipeline stalls due to data hazards?

(a) Data forwarding
(b) Branch prediction
(c) Out-of-order execution
(d) Instruction reordering

Correct Option: (a) Data forwarding
Explanation: Data forwarding (also known as bypassing) resolves data hazards by directly passing data from one pipeline stage to another without writing it back to the register file.

Question 55

Which of the following cache organizations uses fewer bits for indexing?

(a) Direct-mapped cache
(b) 2-way set-associative cache
(c) 4-way set-associative cache
(d) Fully associative cache

Correct Option: (a) Direct-mapped cache
Explanation: Direct-mapped cache uses the fewest bits for indexing, as each block of memory maps to exactly one cache line.

Question 56

In a 5-stage pipeline, if a branch instruction is encountered in the decode stage, it can cause:

(a) A data hazard
(b) A control hazard
(c) A structural hazard
(d) A pipeline stall

Correct Option: (b) A control hazard
Explanation: Control hazards occur when the processor is unsure of which instruction to execute next due to a branch instruction.

Question 57

Which of the following operations is most likely to benefit from a SIMD (Single Instruction, Multiple Data) processor?

(a) Matrix multiplication
(b) String comparison
(c) File I/O operations
(d) Sorting operations

Correct Option: (a) Matrix multiplication
Explanation: SIMD processors excel at performing the same operation on multiple data elements simultaneously, making them ideal for operations like matrix multiplication.

Question 58

Which of the following is a characteristic of a CISC processor?

(a) A large number of registers
(b) A small number of complex instructions
(c) A small number of addressing modes
(d) High performance per clock cycle

Correct Option: (b) A small number of complex instructions
Explanation: CISC processors typically have a larger instruction set with complex instructions, unlike RISC processors, which have a smaller instruction set.

Question 59

Which of the following factors can reduce the efficiency of a pipelined processor?

(a) Higher clock speeds
(b) Pipeline hazards
(c) Higher number of pipeline stages
(d) Increased cache size

Correct Option: (b) Pipeline hazards
Explanation: Pipeline hazards (data, control, and structural hazards) can introduce delays and reduce the efficiency of the pipeline.

Question 60

Which of the following addressing modes uses the contents of a register as an address to access memory?

(a) Immediate addressing
(b) Register addressing
(c) Indirect addressing
(d) Direct addressing

Correct Option: (c) Indirect addressing
Explanation: In indirect addressing, the address of the operand is stored in a register, and the processor uses this register to access memory.