Computer Architecture MCQ Quiz

1. What is the key difference between architecture and microarchitecture?

A. Microarchitecture refers to the overall structure of the system, while architecture refers to the hardware implementation.
B. Architecture is the overall system design, while microarchitecture refers to the specific implementation of the architecture.
C. Architecture deals with software, while microarchitecture deals with hardware.
D. Microarchitecture is a part of ISA.

2. Which of the following is NOT a machine model?

A. Harvard Architecture
B. Von Neumann Architecture
C. ARM Cortex-M
D. Dataflow Machine

3. In a pipelined processor, what type of hazard occurs when two instructions require the same hardware resource at the same time?

A. Data Hazard
B. Control Hazard
C. Structural Hazard
D. Branch Hazard

4. Which of the following is an example of a data hazard?

A. Load-Store Dependency
B. Write-After-Write Dependency
C. Branch Misprediction
D. Fetch-Decode Dependency

5. What is the main purpose of Instruction Set Architecture (ISA)?

A. Defines the specific way hardware resources are utilized
B. Defines the programmer-visible machine interface
C. Determines the instruction fetch stage in the pipeline
D. Directly controls the hardware design

6. A microcoded microarchitecture is most associated with which concept?

A. Complex Instruction Set Computing (CISC)
B. Pipelining
C. Branch Prediction
D. Out-of-order execution

7. Which of the following is NOT a structural hazard?

A. Memory read-write conflict
B. Register write conflict
C. Branch Misprediction
D. ALU conflict

8. What is the function of pipeline stalls?

A. Increase the throughput of the pipeline
B. Resolve data hazards
C. Introduce hazards in the pipeline
D. Decrease control dependencies

9. Which of the following is a control hazard?

A. Instruction Fetch
B. Branch Misprediction
C. Write-After-Read Hazard
D. Cache Miss

10. What is the purpose of branch prediction in a pipelined processor?

A. To avoid pipeline stalls due to incorrect instruction fetches
B. To increase the number of pipeline stages
C. To decrease the instruction memory size
D. To increase clock speed

11. What is a cache miss?

A. When data is found in the cache
B. When the cache does not contain the requested data
C. When the cache fails to store data
D. When multiple cache blocks are required simultaneously

12. Which of the following cache mapping techniques is simplest?

A. Direct Mapped Cache
B. Fully Associative Cache
C. Set-Associative Cache
D. Virtual Cache

13. What is a pipeline hazard?

A. A condition that causes a pipeline to stall or operate incorrectly
B. A faster pipeline stage
C. A hazard due to improper data fetching
D. A misalignment in the instruction cache

14. What is the advantage of pipelining in CPU design?

A. Reduces clock speed
B. Increases instruction throughput
C. Reduces the number of instructions
D. Eliminates control hazards

15. What is the primary function of the cache memory?

A. Increase the size of memory
B. Reduce memory access time
C. Store more instructions
D. Reduce clock cycles

16. Which cache replacement policy is most commonly used in modern processors?

A. Least Recently Used (LRU)
B. First-In-First-Out (FIFO)
C. Random Replacement
D. Least Frequently Used (LFU)

17. What does the term 'write-back cache' mean?

A. Data is written to cache and main memory simultaneously
B. Data is written to cache and only updated in main memory when replaced
C. Data is only written to main memory
D. Data is written to a backup cache

18. Which of the following defines a 'data hazard' in a pipelined architecture?

A. Incorrect instruction fetch
B. Dependency on the result of a previous instruction
C. Incorrect branch prediction
D. Incorrect memory access

19. What is the benefit of using a set-associative cache over a direct-mapped cache?

A. Faster access time
B. Fewer cache misses
C. Simplified cache control logic
D. Reduced power consumption

20. In a 5-stage pipeline, which stage handles the execution of the instruction?

A. Instruction Decode
B. Memory Access
C. Instruction Fetch
D. Execution

21. What is the role of the Instruction Fetch (IF) stage in a pipeline?

A. Decodes the instruction
B. Fetches the instruction from memory
C. Writes results to registers
D. Executes the instruction

22. What is the primary difference between a superscalar and a scalar processor?

A. Superscalar processors issue multiple instructions per cycle
B. Scalar processors are more power-efficient
C. Superscalar processors have longer pipelines
D. Scalar processors handle floating-point operations better

23. Which of the following is a benefit of out-of-order execution?

A. Reduced branch misprediction penalty
B. Increased memory size
C. Improved instruction-level parallelism
D. Lower clock cycles per instruction

24. Which memory technology is typically used for cache memory?

A. Dynamic RAM (DRAM)
B. Flash Memory
C. Static RAM (SRAM)
D. Magnetic RAM (MRAM)

25. What does ISA stand for in computer architecture?

A. Instruction Set Architecture
B. Input Set Architecture
C. Integrated System Architecture
D. Internal Storage Architecture

26. What is the main purpose of using a pipeline in CPU design?

A. Increase clock frequency
B. Increase instruction throughput
C. Decrease power consumption
D. Simplify the control unit

27. Which of the following is NOT a type of control hazard?

A. Jump
B. Branch
C. Cache miss
D. Conditional branch

28. Which pipeline stage is responsible for accessing memory during a load or store operation?

A. Fetch
B. Execute
C. Memory
D. Writeback

29. What does a 'pipeline bubble' refer to?

A. A full pipeline
B. A clock cycle with no instruction in the pipeline
C. An instruction skip in the pipeline
D. A branch misprediction

30. What is the primary purpose of branch prediction in modern processors?

A. To reduce cache misses
B. To minimize pipeline stalls caused by branches
C. To improve memory access speeds
D. To speed up floating-point operations

31. In microcoded microarchitecture, what is the role of the control store?

A. It holds the machine code of instructions
B. It stores microinstructions to control the datapath
C. It manages memory access
D. It decodes instructions

32. Which hazard occurs when the result of one instruction is not available to another in the pipeline?

A. Control hazard
B. Data hazard
C. Structural hazard
D. Memory hazard

33. Which cache mapping technique provides the fastest cache lookup?

A. Fully associative
B. Direct-mapped
C. Set-associative
D. Random-mapped

34. What does CPI stand for in processor performance evaluation?

A. Clocks per instruction
B. Cycles per instruction
C. Cache per instruction
D. Control per instruction

35. What type of cache write policy writes the data to both the cache and the main memory?

A. Write-back
B. Write-through
C. Write-allocate
D. Write-around

36. What happens during a structural hazard in a pipelined processor?

A. An incorrect instruction is fetched
B. Two instructions try to use the same hardware resource at the same time
C. The result of an instruction is not available
D. The cache misses an access

37. Which type of pipeline hazard is caused by branches and jumps?

A. Data hazard
B. Control hazard
C. Structural hazard
D. Memory hazard

38. What is the primary advantage of a set-associative cache over a direct-mapped cache?

A. Reduced complexity
B. Increased cache size
C. Fewer conflict misses
D. Faster access time

39. In which cache level is the miss penalty generally the highest?

A. L1 cache
B. L2 cache
C. L3 cache
D. Main memory

40. What is the benefit of a multi-level cache hierarchy in processors?

A. It simplifies memory management
B. It reduces the memory latency seen by the processor
C. It increases cache capacity
D. It reduces power consumption

41. Which type of data hazard is resolved by forwarding or bypassing techniques?

A. RAW (Read After Write)
B. WAR (Write After Read)
C. WAW (Write After Write)
D. Memory hazard

42. In which scenario is a memory-mapped I/O more efficient than port-mapped I/O?

A. When large amounts of data need to be transferred
B. When I/O operations are infrequent
C. When the CPU is busy with other tasks
D. When addressing large numbers of I/O devices

43. Which of the following is true for out-of-order execution in modern processors?

A. Instructions are executed in the exact order they are fetched
B. Instructions can be executed in an order that minimizes delays
C. Out-of-order execution leads to more stalls
D. It increases the need for branch prediction

44. What is the main role of the Translation Lookaside Buffer (TLB) in a processor?

A. It stores frequently accessed data
B. It caches page table entries to reduce memory access time
C. It holds decoded instructions
D. It manages context switching

45. Which of the following is not a valid cache replacement policy?

A. Least Recently Used (LRU)
B. Most Recently Used (MRU)
C. First In First Out (FIFO)
D. Least Frequently Used (LFU)

46. Which of the following cache coherence protocols is used in multiprocessor systems?

A. MESI (Modified, Exclusive, Shared, Invalid)
B. Write-through
C. Write-back
D. Direct-mapped

47. What type of memory is typically used for the L1 cache?

A. DRAM
B. SRAM
C. Flash memory
D. ROM

48. Which of the following is a disadvantage of a write-back cache policy?

A. Increased latency due to write operations
B. Higher complexity in cache control
C. Increased traffic to the main memory
D. Risk of data loss during power failure

49. Which instruction allows a processor to transition from user mode to kernel mode in an operating system?

A. sysenter
B. int
C. cli
D. sti

50. Which bus is responsible for transferring data between the CPU and the memory in a computer system?

A. Data bus
B. Address bus
C. Control bus
D. I/O bus